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datasheet 6V49205B revision p 08/10/15 1 ?2015 integrated device technology, inc. freescale p10xx and p20xx system clock w/selectable ddr frequency 6V49205B general description the 6V49205B is a main clock for freescale p10xx and p20xx-based systems. it has a selectable system ccb clock and 2 ddrclk speeds ? 100m or 66.66m. the 6V49205B also provides lp-hcsl pcie outputs for low power and reduced board space. output features ? 1 - sys_ccb 3.3v lvcmos output @ 100m/83.33m/ 80m/66.66m ? 1 - ddrclk 3.3v lvcmos output @ 100m or 66.66m 1 ? 1 - 125m 3.3v lvcmos output ? 6 - lp-hcsl pcie pairs selectable @ 100m or 125m ? 6 - 25mhz 3.3v lvcmos outputs ? 2 - 2.048m 3.3v lvcmos outputs ? 2 - usb 3.3v lvcmos outputs @12m or 24m key specifications ? pcie gen1-2-3 compliant ? <3p rms phase noise on ref outputs recommended application system clock for freescale p10xx and p20xx-based designs features ? replaces 11 crystals, 2 oscilla tors and 3 clock generators; lowers cost, power and area ? lp-hcsl pcie outputs reduce termination resistors by 50% while saving 67% power; reduces board area and power ? industrial temperature r ange operation; supports demanding environmental conditions ? advanced 3.3v cmos proc ess; high-performance, low-power ? supports independent spread spectrum on sys_ccb/ddrclk and pcie outputs ? space-saving 7x7mm 48-pin vfqfpn with 0.5mm pad pitch; reduced board space without the need for fine-pitch assembly techniques block diagram note 1 : for ddr clock: processor core and i/o supply rails must be ra mped with vdd3p3 or earlier. clock signal will be clamped low and output clock will be 100mhz if this is no t followed (see diagram below). gnd crystal oscillator pll1 (ss) 25mhz crystal x1 x2 pll3 (non- ss) ref(5:0) ddrclk sys_ccb pll4 (ss) pcie_lr(5:0) control logic sclk 2.048m(1:0) usb_clk(2:1) ^fs0 pll2 (non- ss) 125m ^fs1 ^sel100#_66 ^selpcie125#_100 sdata 100mhz ddrclk r40 r39 vdd3p3 10k 10k
freescale p10xx and p20xx system clock w/selectable d dr frequency 2 revision p 08/10/15 6V49205B datasheet pin assignments x2_25 1 48 v ddref x1_25 2 47 sdata gndref 3 46 sclk ref5 4 45 gndddr ref4 5 44 ^sel100#_66/ ddrclk ref3 6 43 vddddr vddref 7 42 avddsys gndref 8 41 sys_ccb ref2 9 40 gndsys ref1 10 39 gndpcie ^selpcie125#_100/ref0 11 38 pciet_lr5 avdd12_24 12 37 pciec_lr5 ^fs0/usb_clk1 13 36 pciet_lr4 ^fs1/usb_clk2 14 35 pciec_lr4 gnd12_24 15 34 gndpcie gnd2.048 16 33 avddpcie ck2.048_0 17 32 pciet_lr3 ck2.048_1 18 31 pciec_lr3 vdd2.048 19 30 pciet_lr2 avdd125 20 29 pciec_lr2 125m 21 28 gndpcie gnd125m 22 27 vddpcie pciet_lr0 23 26 pciet_lr1 pciec_lr0 24 25 pciec_lr1 48-pin tssop ^ indicates internal 100kohm pull up resistor 6V49205B vddref sdata sclk gndddr ^sel100#_66/ddrclk vddddr avddsys sys_ccb gndsys gndpcie pciet_lr5 pciec_lr5 48 47 46 45 44 43 42 41 40 39 38 37 x2_25 1 36 pciet_lr4 x1_25 2 35 pciec_lr4 gndref 3 34 gndpcie ref5 4 33 avddpcie ref4 5 32 pciet_lr3 ref3 6 31 pciec_lr3 vddref 7 30 pciet_lr2 gndref 8 29 pciec_lr2 ref2 9 28 gndpcie ref1 10 27 vddpcie ^selpcie125#_100/ref0 11 26 pciet_lr1 avdd12_24 12 25 pciec_lr1 13 14 15 16 17 18 19 20 21 22 23 24 ^fs0/usb_clk1 ^fs1/usb_clk2 gnd12_24 gnd2.048 ck2.048_0 ck2.048_1 vdd2.048 avdd125 125m gnd125m pciet_lr0 pciec_lr0 6V49205B ^ indicates internal 100kohm pull up resistor 48-pin vfqfpn
revision p 08/10/15 3 freescale p10xx and p20xx system clock w/sel ectable ddr frequency 6V49205B datasheet pin descriptions pin # pin name pin type description 1 x2_25 out crystal output, nominally 25.00mhz. 2 x1_25 in crystal input, nominally 25.00mhz. 3 gndref pwr ground pin for the ref outputs. 4 ref5 out copy of crystal input 5 ref4 out copy of crystal input 6 ref3 out copy of crystal input 7 vddref pwr ref, xtal power supply, nominal 3.3v 8 gndref pwr ground pin for the ref outputs. 9 ref2 out copy of crystal input 10 ref1 out copy of crystal input 11 ^selpcie125#_100/ref0 i/o latched input to select the pcie output frequency/ref0 output. 0 = 125m 1 = 100m 12 avdd12_24 pwr power for 12_24mhz pll core, and outputs. nominal 3.3v 13 ^fs0/usb_clk1 i/o frequency select latch for sys_ccb / 12 or 24mhz usb clock output. 3.3v. this pin has an internal pull up resistor. 14 ^fs1/usb_clk2 i/o frequency select latch for sys_ccb / 12 or 24mhz usb clock output. 3.3v. this pin has an internal pull up resistor. 15 gnd12_24 pwr ground pin for 12_24m outputs. 16 gnd2.048 pwr ground pin for 2.048m outputs. 17 ck2.048_0 out 2.048m output, nominal 3.3v. 18 ck2.048_1 out 2.048m output, nominal 3.3v. 19 vdd2.048 pwr power supply for 2.048m outputs, nominal 3.3v. 20 avdd125 pwr power for 125mhz pll core and output, nominal 3.3v 21 125m out 125m output, nominal 3.3v. 22 gnd125m pwr ground pin for 125m outputs. 23 pciet_lr0 out true clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 24 pciec_lr0 out complement clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 25 pciec_lr1 out complement clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 26 pciet_lr1 out true clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 27 vddpcie pwr power supply for pci express outputs, nominal 3.3v 28 gndpcie pwr ground pin for the pcie outputs. 29 pciec_lr2 out complement clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 30 pciet_lr2 out true clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 31 pciec_lr3 out complement clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 32 pciet_lr3 out true clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 33 avddpcie pwr analog power supply for pci express clocks, nominal 3.3v 34 gndpcie pwr ground pin for the pcie outputs. 35 pciec_lr4 out complement clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 36 pciet_lr4 out true clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 37 pciec_lr5 out complement clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 38 pciet_lr5 out true clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 39 gndpcie pwr ground pin for the pcie outputs. 40 gndsys pwr ground pin for the sys_ccb output 41 sys_ccb out system ccb clock output 42 avddsys pwr analog power supply for sys_ccb clock and outputs, nominal 3.3v 43 vddddr pwr power supply for ddr clock output, nominal 3.3v 44 ^sel100#_66/ddrclk i/o latched input to select the ddr output frequency/ddrclk output. see note regarding system power sequencing. 0 = 100m 1 = 66.666m 45 gndddr pwr ground pin for the ddr outputs. 46 sclk in clock pin of smbus circuitry. 47 sdata i/o data pin for smbus circuitry. 48 vddref pwr ref, xtal power supply, nominal 3.3v
freescale p10xx and p20xx system clock w/selectable d dr frequency 4 revision p 08/10/15 6V49205B datasheet table 1: pciex spread table (selectable via smbus) table 2: sys_ccb an d ddr spread table (selectable via smbus) table 3: sys_ccb frequency select table (latched and selectable via smbus) table 4: slew rate selection table (selectable via smbus, bytes 3 and 4) table 5: pci express amplitude control fs1 / b4b3 fs0 / b4b2 sys_ccb 00 66.66 mhz 01 100 mhz 10 80 mhz 11 83.333 mhz msb lsb slew rate 0 0 hi-z 0 1 1.5 1 0 2.1 1 1 2.4 selpcie125#_100 b6b4 b0b4 b0b3 spread % 0 (125mhz) x x no spread 1 (100mhz) 0 0 no spread (default) 1 (100mhz) 0 1 down -0.5% 1 (100mhz) 1 0 down -0.75% 1 (100mhz) 1 1 no spread *once in spread mode, do not return to non spread without reset b0b7 b0b6 b0b5 spread % 0 0 0 no spread (default) 001 down -0.5% 010 down -0.75% 011 down -0.25% 100 down -1% 101 down -1.25% 110 down -1.5% 111 down -2% b5b7 b5b6 pci ex p ress am p litude 0 0 700mv 0 1 800mv 1 0 900mv 1 1 1000mv
revision p 08/10/15 5 freescale p10xx and p20xx system clock w/sel ectable ddr frequency 6V49205B datasheet absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 6V49205B. these ratings, which are standard values for idt commercially rated parts, are stress ratings on ly. functional operation of the device at these or any other conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods ca n affect product reliability. electrical parameters are guaran teed only over the recommended operating temperature range. electrical characteristics - input/ supply/common output dc parameters parameter symbol conditions min typ max units notes maximum supply voltage vddxxx supply voltage 4.6 v 1 maximum input voltage v ih referenced to gnd vdd + 0.5 v 1 minimum input voltage v il referenced to gnd gnd - 0.5 v 1 storage temperature ts - -65 150 c junctiontemperature tj - 125 c 1 input esd protection esd prot human body model 2000 v 1 1 operation under these conditions is neither implied, nor guaranteed. notes on absolute max parameters t amb = -40 to +85c; v dd = 3.3 v +/-5%, all outputs driving test loads (unless noted otherwise). parameter symbol conditions min typ max units notes ambient operating temp t amb --402585c supply voltage vddxxx supply voltage 3.135 3.3 3.465 v power supply ramp time t pwrrmp power supply ramp must be montonic 4 ms latched input high voltage v ih_li single-ended latched inputs 2.1 v dd + 0.3 v latched input low voltage v il_li single-ended latched inputs v ss - 0.3 0.8 v input leakage current i in v in = v dd , v in = gnd -5 5 ua 2 operating supply current i ddop3.3 all outputs loaded and running 119 155 ma input frequency f i 23 25 27 mhz 3 pin inductance l pin 57 nh c in logic inputs 1.5 3 5 pf c out output pin capacitance 5 6 pf c inx x1 & x2 pins 5 6 pf clk stabilization t stab from vdd power-up or de-assertion of pd to 1st clock 3.2 5 ms tfall_s e t fall 10 ns 1 trise_se t rise 10 ns 1 smbus voltage v dd 2.7 3.3 v low-level output voltage v olsmb @ i pullup 0.4 v current sinking at v olsmb = 0.4 v i pullup smb data pin 4 ma sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns smbus operating frequency f smbus 400 khz 1 signal is required to be monotonic in this region. 2 input leakage current does not include inputs with pull-up or pull-down resistors input capacitance fall/rise time of all 3.3v control inputs from 20-80% notes on dc parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 3 for margining purposes only. normal operation should have fin =25mhz
freescale p10xx and p20xx system clock w/selectable d dr frequency 6 revision p 08/10/15 6V49205B datasheet ac electrical characteristics - low power hcsl-compatib le pcie outputs electrical characteris tics - phase jitter, pc ie outputs at 100mhz parameter symbol conditions min typ max units notes mhz 2,3 mhz 2,3 ppm ssof f pcie 100mhz or 125mhz ppm 1,2 ppm sson pcie @ -0.5% spread, 100mhz only ppm 1,2 rising/falling edge slew rate t slew differential measurement 2.2 4.1 5.7 v/ns 1,3,6 slew rate variation t slvar single-ended measurement 1 20 % 1,6 maximum output voltage v high includes overshoot 793 1150 mv 6,7 minimum output voltage v low includes undershoot -300 -22 mv 6,7 differential voltage swing v swing differential measurement 300 mv 1,6 crossing point voltage v xabs single-ended measurement 300 419 550 mv 1,4,6 crossing point variation v xabsvar single-ended measurement 115 140 mv 1,4,5 duty cycle d cyc differential measurement 45 50.1 55 % 1 pcie jitter - cycle to cycle pcie jc2c differential measurement 36 125 ps 1 pcie[5:0] skew t skewpcie50 differential measurement 1172 1500 ps 1,6,8 spread spectrum modulation frequency f ssmod triangular modulation 30 31.5 33 khz notes for pcie clocks: 1 guaranteed by design and characterization, not 100% tested in production. 2 clock frequency specifications are guaranteed assuming that ref is at 25mhz 3 slew rate measured through v_swing voltage range centered about differential zero 4 vcross is defined at the voltage where clock = clock#. 5 only applies to the differential rising edge (clock rising, clock# fa lling.) 6 at default smbus settings. 7 the freescale p-series cpu's have internal terminations on their serdes reference clock inputs. the resulting amplitude at the se inputs w ill be 1/2 of the values listed, which are well within the 800mv freescale specification for these inputs. 8 this value includes an intentional output-to-output skew of approximately 250ps. synthesis error 0 +/-100 clock frequency f spread off 100.00 125.00 parameter symbol conditions min typ max industry spec limit units notes t jp hpcie1 pcie gen 1 phase jitter 35 56 86 ps 1,2,3 t jphpcie2lo pcie gen 2 phase jitter lo-band content 1.6 2.4 3 ps (rms) 1,2,3 t jphpcie2hi pcie gen 2 phase jitter hi-band content 1.9 2.8 3.1 ps (rms) 1,2,3 t jphpcie3 pcie gen 3 phase jitter 0.5 0.83 1 ps (rms) 1,2,3 notes on phase jitter: 2 sample size of at least 100k cycles. this fi g ures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1 -12 3 applies to pcie outputs @ default amplitude and 100mhz with spread off or at -0.5%. 1 see http://www.pcisig.com for complete specs. guaranteed by design and characterization, not tested in production. jitter, phase
revision p 08/10/15 7 freescale p10xx and p20xx system clock w/sel ectable ddr frequency 6V49205B datasheet electrical characteristics - ddr clock electrical characteristics - sys_ccb electrical characteristics - 125m parameter symbol conditions min typ max units notes f ddr66.66 sel100#_66 = 1, v t = ovdd/2 v mhz 2,3,6 f ddr100 sel100#_66 = 0, v t = ovdd/2 v mhz 2,3,6 ppm ssof f spread off ppm 1,2,5 ppm sson spread on ppm 1,2,5 output high voltage v oh v oh at the selected operating frequency 2.4 v 1 output low voltage v ol v ol at the selected operating frequency 0.4 v 1 t slew00 '00' = hi-z v/ns t slew01 '01' slow slew rate (averaging on) 1.1 1.6 2.3 v/ns 1,3,8 t slew10 '10' fast slew rate (averaging on) 1.6 2.3 3.2 v/ns 1,3,8 t slew11 '11' fastest slew rate (averaging on) 1.8 2.7 3.7 v/ns 1,3,8 duty cycle d t1 v t = ovdd/2 v 40 51.4 60 % 1,6 jitter, peak period jitter t jpeak v t = ovdd/2 v 96 150 ps 1,6 phase noise t phasenoise -56dbc 10 500 khz 1,7 ac input swing limits @ 3.3v ov dd v ac this is the difference between vol and voh at the selected operating frequency. 1.9 3.4 v 1 spread spectrum modulation frequency f ssmod triangular modulation 30 32.3 60 khz slew rate vddo = 3.3v hi-z ddr clock fr equency 66.666 100.00 synthesis error 0 +/-150 parameter symbol conditions min typ max units notes fs(1:0) = 00, vt = ovdd/2 v mhz 2,3,6 fs(1:0) = 01, vt = ovdd/2 v mhz 2,3,6 fs(1:0) = 10, vt = ovdd/2 v mhz 2,3,6 fs(1:0) = 11, vt = ovdd/2 v mhz 2,3,6 ppm ssof f spread off ppm 1,2,5 ppm sson spread on ppm 1,2,5 output high voltage v oh v oh at the selected operating frequency 2.4 v 1 output low voltage v ol v ol at the selected operating frequency 0.4 v 1 t slew00 '00' = hi-z v/ns t slew01 '01' slow slew rate (averaging on) 0.8 1.4 2.1 v/ns 1,3,8 t slew10 '10' fast slew rate (averaging on) 0.9 1.6 2.5 v/ns 1,3,8 t slew11 '11' fastest slew rate (averaging on) 1.1 1.9 3.1 v/ns 1,3,8 duty cycle d t1 v t = ovdd/2 v 40 51.4 60 % 1,6 jitter, peak period jitter t jpeak v t = ovdd/2 v, ssc < 0.75% 116 150 ps 1 phase noise t phasenoise -56dbc 10 500 khz 1,7 ac input swing limits @ 3.3v ov dd v ac this is the difference between vol and voh at the selected operating frequency. 1.9 v 1 spread spectrum modulation frequency f ssmod triangular modulation 0 31.5 60 khz hi-z slew rate vddo = 3.3v 83.333 synthesis error 0 +/-150 clock frequency f sy s_ccb 66.666 100.00 80.00 parameter symbol conditions min typ max units notes clock frequency f 125m v t = ovdd/2 v ns 2,3,6 synthesis error ppm ppm 1,2,5 output high voltage v oh v oh at the selected operating frequency 2.2 v 1 output low voltage v ol v ol at the selected operating frequency 0.5 v 1 rise/fall time vddo = 3.3v t rf125m3.3v measured between 0.6v and 2.7v 0.7 1 ns 1,3 duty cycle d t1 v t = ovdd/2 v 47 52 53 % 1 jitter, peak period jitter t jpeak v t = ovdd/2 v 150 ps 1 0 125.00
freescale p10xx and p20xx system clock w/selectable d dr frequency 8 revision p 08/10/15 6V49205B datasheet electrical charac teristics - ref(5:0) electrical character istics - usb_clk(2:1) electrical character istics - 2.048m(1:0) parameter symbol conditions min typ max units notes clock frequency f v t = ovdd/2 v mhz 2,3 crystal frequency error ppm including all aging and tuning effects -50 50 ppm 1,2 output high voltage v oh v oh at the selected operating frequency 2.2 v 1 output low voltage v ol v ol at the selected operating frequency 0.4 v 1 slew rate vddo 3 3v t slew '00' = hi-z 1.0 1.7 2.7 v/ns 1,3,4 duty cycle d t1 v t = ovdd/2 v 40 51 60 % 1 pin to pin skew t skew v t = 1.5 v, odd/even outputs have an intentional 180degree phase shift. ps 1 jitter, peak period jitter t jpeak v t = ovdd/2 v 78 200 ps 1 jitter, phase t jphase (12khz-5mhz), v t = 1.5 v 1.7 3 ps rms 1 n/a 25.00 parameter symbol conditions min typ max units notes mhz 2,3 mhz 2,3 synthesis error ppm ppm 1,2,5 output high voltage v oh v oh at the selected operating frequency 2.2 v 1 output low voltage v ol v ol at the selected operating frequency 0.4 v 1 t slew00 '00' = hi-z v/ns t slew01 '01' slow slew rate (averaging on) 1.0 1.4 1.8 v/ns 1,3,4 t slew10 '10' fast slew rate (averaging on) 1.5 2.0 2.7 v/ns 1,3,4 t slew11 '11' fastest slew rate (averaging on) 1.8 2.3 3.1 v/ns 1,3,4 duty cycle d t1 v t = ovdd/2 v 45 50.3 55 % 1 jitter, rms t jrms 12khz to nyquist 23 120 ps 1 jitter, cycle to cycle t jcyc-cyc v t = ovdd/2 v 142 350 ps 1 slew rate vddo = 3.3v hi-z 24.00 0 clock frequency f usb_clk v t = ovdd/2 v 12.00 parameter symbol conditions min typ max units notes clock frequency f usb_clk v t = ovdd/2 v mhz 2,3,6 synthesis error ppm ppm 1,2,5 output high voltage v oh v oh at the selected operating frequency 2.2 v 1 output low voltage v ol v ol at the selected operating frequency 0.4 v 1 t slew00 '00' = hi-z v/ns t slew01 '01' slow slew rate (averaging on) 1.1 1.7 2.5 v/ns 1,3,4 t slew10 '10' fast slew rate (averaging on) 1.6 2.3 3.2 v/ns 1,3,4 t slew11 '11' fastest slew rate (averaging on) 1.8 2.6 3.6 v/ns 1,3,4 duty cycle d t1 v t = ovdd/2 v 45 46.7 55 % 1 pin to pin skew t skew v t = ovdd/2 v 108 250 ps 1 jitter, rms t jrms 12khz to nyquist 47 70 ps 1 jitter, peak period jitter t jpeak v t = ovdd/2 v 170 250 ps 1 notes for single-ended clocks: 1 guaranteed by design and characterization, not 100% tested in production. 2 clock frequency specifications are guaranteed assuming that ref is at 25mhz 3 at default smbus settings 4 measured betweeen 20% and 80% of ovdd 5 this is the frequency error with respect to the crystal frequency. 6 measured at the rising and/or fa lling edge at ovdd/2 v. 7 phase noise is calculated as the fft of the tie jitter. 8 slew rate is measured from 0.3 v ac at the center of peak to peak voltage at the clock input. hi-z slew rate vddo = 3.3v 2.048 0
revision p 08/10/15 9 freescale p10xx and p20xx system clock w/sel ectable ddr frequency 6V49205B datasheet general smbus serial interf ace information for 6V49205B how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledge each byte one at a time ? controller (host) sends a stop bit note: i 2 c compatible . native mode is smbus block mode protocol. to use i 2 c byte mode set the 2^7 bit in the command byte. no byte count is used. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address d2 (h) wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address d2 (h) wr write ack beginning byte = n ack rt repeat start slave address d3 (h) rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
freescale p10xx and p20xx system clock w/selectable d dr frequency 10 revision p 08/10/15 6V49205B datasheet byte 0 frequency and spread select register bit name description type default 7 ss4 rw 0 6 ss3 rw 0 5 ss2 rw 0 4 ss1 rw 0 3 ss0 rw 0 2 ref_5_en output enable for ref_5 rw 1 1 ref_4_en output enable for ref_4 rw 1 0 ref_3_en output enable for ref_5 rw 1 byte 1 output enable register bit name description type default 7 ref_2_en output enable for ref_2 rw 1 6 ref_1_en output enable for ref_1 rw 1 5 ref_0_en output enable for ref_0 rw 1 4 usb_clk1_en output enable for usb_clk1 rw 1 3 usb_clk2_en output enable for usb_clk2 rw 1 2 ck2.048_0_en output enable for ck2.048_0 rw 1 1 ck2.048_1_en output enable for ck2.048_1 rw 1 0 ddrclk_en output enable for ddrclk rw 1 byte 2 output enable register bit name description type default 7 sys_ccb_en output enable for sys_ccb rw 1 6 pcie5_en output enable for pcie5 rw 1 5 pcie4_en output enable for pcie4 rw 1 4 pcie3_en output enable for pcie3 rw 1 3 pcie2_en output enable for pcie2 rw 1 2 pcie1_en output enable for pcie1 rw 1 1 pcie0_en output enable for pcie0 rw 1 0 125m_en output enable for 125m rw 1 byte 3 slew rate control register bit name description type default 7 usb1_slew1 rw 0 6 usb1_slew0 rw 1 5 usb2_slew1 rw 0 4 usb2_slew0 rw 1 3 ck2.048_slew1 rw 1 2 ck2.048_slew0 rw 1 1 sys_ccb_slew1 rw 0 0 sys_ccb_slew0 rw 1 byte 4 slew rate control register bit name description type default 7 66m_slew1 rw 0 6 66m_slew0 rw 1 5 0 4 1 3fs1 rw latch 2fs0 rw latch 1 usb1_fsel usb_clk1 clock frequency select rw 0 0 usb2_fsel usb_clk2 clock frequency select rw 1 sys_ccb and ddrclk spread selection table see table 2: sys_ccb and ddrclk spread table ddrclk slew rate control see table 4: slew rate selection table sys_ccb frequency select latch see table 3: sys_ccb frequency selection 12mhz 24mhz 12mhz 24mhz reserved reserved ck2.048_0 and ck2.048_1 slew rate control see table 4: slew rate selection table sys_ccb slew rate control see table 4: slew rate selection table 01 01 usb_clk1 slew rate control see table 4: slew rate selection table usb_clk2 slew rate control see table 4: slew rate selection table output disabled output enabled output disabled output enabled output disabled output enabled output disabled output enabled output disabled output enabled output disabled output enabled 01 output disabled output enabled output disabled output enabled output disabled output enabled 01 output disabled output enabled output disabled output enabled pcie spread selection table see table 1: pcie spread table output disabled output enabled output disabled output enabled output disabled output enabled 01 output disabled output enabled output disabled output enabled output disabled output enabled output disabled output enabled output disabled output enabled
revision p 08/10/15 11 freescale p10xx and p20xx system clock w/sel ectable ddr frequency 6V49205B datasheet recommended crystal char acteristics ( 3225 package) byte 5 is reserved byte 6 pci express amplitude control register bit name description type default 7 pcie_amp1 rw 0 6 pcie_amp0 rw 1 5 sel100#_66 ddrclk latch select r latch 4 selpcie125#_100 pci express latch select r latch 3 reserved reserved rw 0 2 reserved reserved rw 1 1 reserved reserved rw 0 0 reserved reserved rw 1 byte 7 revision and vendor id register bit name description type default 7 rev id r 0 6 rev id r 0 5 rev id r 0 4 rev id r 1 3 vendor id r 0 2 vendor id r 0 1 vendor id r 0 0 vendor id r 1 byte 8 byte count register bit name description type default 7 bc7 rw 0 6 bc6 rw 0 5 bc5 rw 0 4 bc4 rw 0 3 bc3 rw 0 2 bc2 rw 1 1 bc1 rw 0 0 bc0 rw 1 byte count programming b(7:0) -- 01 -- -- -- -- -- -- -- 01 writing to this register will configure how many bytes will be read back. 01 -- pci express amplitude control see table 5: pcie amplitude selection table 100mhz 66mhz 125mhz 100mhz -- -- revision id vendor id -- parameter value units notes frequency 25 mhz 1 resonance mode fundamental - 1 frequency tolerance @ 25c 20 ppm max 1 frequency stability, ref @ 25c over operating temperature range 20 ppm max 1 temperature range (commerical) 0~70 c 1 temperature range (industrial) -40~85 c 1 equivalent series resistance (esr) 50 ? 5 ppm max 1 notes: 1. idt 603-25-150 or fox 603-25-150.
freescale p10xx and p20xx system clock w/selectable d dr frequency 12 revision p 08/10/15 6V49205B datasheet test loads thermal characteristi cs (48-tssop) pag48 thermal characteristi cs (48-vfqfpn) nlg48 marking diagrams notes: 1. ?$? is the mark code. 2. yyww is the last two digits of the year, and the week number that the part was assembled. 3. ?g? after the two-letter package code denotes pb free package. 4. ?i? denotes industrial temperature range. 5. bottom marking for tssop: country of origin if not usa. rs=33 ? low-power hcsl output rs=33 ? low-power differential output test load 2pf 2pf zo= differential impedance device rs=39 ? zo test load cl=4.7pf except 3v66 outputs where cl=15pf single-ended output device parameter symbol conditions pkg typ value units notes jc junction to case 28 c/w 1 c/w 1 c/w 1 c/w 1 ja3 junction to air, 3 m/s air flow 51 c/w 1 pag48 thermal resistance parameter symbol conditions pkg typ value units notes c/w 1 c/w 1 c/w 1 c/w 1 ja3 junction to air, 3 m/s air flow 22 c/w 1 1 epad soldered to board thermal resistance nlg48 1 24 25 48 idt 6V49205Bpagi yyww$ 48tssop idt6v4 9205bn lgi yyww$ 48vfqfpn
revision p 08/10/15 13 freescale p10xx and p20xx system clock w/sel ectable ddr frequency 6V49205B datasheet package outline and package dimensions (nlg48, 48-pin 7mm x 7mm vfqfpn) millimeters symbol min max a 0.80 0.90 a1 0 0.05 a3 0.20 reference b 0.18 0.30 e 0.50 basic n48 n d 12 n e 12 d x e basic 7.00 x 7.00 d1 5.50 basic e1 5.50 basic d2 5.50 5.80 e2 5.50 5.80 zd 0.75 basic ze 0.75 basic l 0.35 0.45
freescale p10xx and p20xx system clock w/selectable d dr frequency 14 revision p 08/10/15 6V49205B datasheet package outline and package dimensions ( pag48, 48-pin tssop, 6.10 mm body, 0.50 pitch ) package dimensions are kept curre nt with jedec publication no. 95 ordering information ?g? after the two-letter package code denotes pb-free configuration, rohs compliant. part / order number marking shipping packaging package temperature 6V49205Bpagi see page 12 tubes 48-pin tssop -40 ? to +85 ? c 6V49205Bpagi8 tape and reel 48-pin tssop -40 ? to +85 ? c 6V49205Bnlgi see page 12 tray 48-pin vfqfpn -40 ? to +85 ? c 6V49205Bnlgi8 tape and reel 48-pin vfqfpn -40 ? to +85 ? c index area 1 2 48 d e1 e seating plane a1 a a2 e - c - b aaa c ? c l *for reference only. controlling dimensions in mm. millimeters inches* symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.17 0.27 0.007 0.011 c 0.09 0.20 0.0035 0.008 d 12.40 12.60 0.488 0.496 e 8.10 basic 0.319 basic e1 6.00 6.20 0.236 0.244 e 0.50 basic 0.020 basic l 0.45 0.75 0.018 0.030 ? 0 ? 8 ? 0 ? 8 ? aaa -- 0.10 -- 0.004
revision p 08/10/15 15 freescale p10xx and p20xx system clock w/sel ectable ddr frequency 6V49205B datasheet revision history rev. issue date issuer description page # l 9/12/2013 v. chaudhry 1. updated pins 12, 20, 33 and 42 in pinouts and pin descriptions. various m 12/9/2013 r. wade 1. extensive overhaul of electrical tables to more closely align with freescale published specifications. 2. updated electrical tables with characterization data. 3. clarified smbus registers for slew rate controls 4. moved electrical tables in front of smbus for consistency with other data sheets. 5. updated thermal data and added test loads for clarity. 6. updated front page text 7. minor updates to pin names (mainly power and ground) for consistency and clarity 8. move to final various n 6/2/2014 r. wade 1. corrected pin description for pin 44. 3 p 8/10/2015 r. wade 1. updated smbus operating frequency from 100khz minimum to 400khz maximum. 5
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